1. Field of the Invention
The invention relates to computer-aided engineering (CAE) tools for designing and testing electronic systems.
2. Description of the Background Art
Electronic design automation (EDA) tools are used to define and verify prototype systems, such as various application specific integrated circuits (ASICs). Typically, ASICs include digital and/or analog components, which are interconnected electrically to define certain functionality.
Conventional EDA tools provide computer-aided facilities for electronic engineers to define prototype designs, typically by generating either netlist files, which specify components and their interconnections, or hardware description files, which specify prototype system functionality according to a hardware description language (HDL).
Additionally, such EDA tools provide for early functional verification of the prototype definition, e.g., by performing simulation or emulation before a physical prototype system is actually manufactured.
Simulation generally involves executing a computer program which uses models that represent the functionality of a corresponding prototype definition or component. Thus, during simulation, each model behaves as its corresponding part, so as to generate verifiable, imitated functional or logical output signals in response to stimuli applied to the model.
Emulation is another approach for verifying prototype functionality. Through emulation, an operational, equivalent functional representation of the prototype definition is temporarily constructed, either by assembling a "bread-board" of the components and interconnections in the prototype system, or by configuring according to the prototype definition certain reprogrammable logic circuits, such as field programmable gate arrays (FPGAs). Once constructed, the emulated representation may be coupled directly to its intended target system, thereby enabling functional cooperation and verification therebetween.
Conventional simulation and emulation approaches are limited, however, to the extent that neither approach facilitates distributed verification of various, generalized prototype definitions.